1. Field of the Invention
The present invention relates to a duty cycle correction circuit, and more particularly, to a duty cycle correction circuit with wide-frequency working range.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional duty cycle correction circuit 100. As shown in FIG. 1, the duty cycle correction circuit 100 comprises a duty cycle correcting device 110 and a delay lock loop circuit 120. The duty cycle correcting device 110 receives a reference clock signal CLKIN, and accordingly generates a corrected clock signal CLKDCC. The duty cycle of the corrected clock signal CLKDCC is 50%. The delay lock loop circuit 120 is coupled to the duty cycle correcting device 110 for receiving the corrected clock signal CLKDCC and accordingly generating a delayed corrected clock signal CLKOUT. The delay lock loop circuit 120 requires a locking period TL1 for leading the phase of the delayed corrected clock signal CLKOUT to the same phase of the corrected clock signal CLKDCC. The duty cycle correcting device 110 requires a locking period TL2 for leading the phase of the corrected clock signal CLKDCC to the same phase of the reference clock signal CLKIN.
Therefore, according to the description above, the conventional duty cycle correction circuit 100 requires the sum of the locking periods TL1 and TL2 in order to lock the phase of the outputted delayed corrected clock signal CLKOUT to the same phase of the reference clock signal CLKIN, which easily causes unstable status of the output clock signal CLKOUT because of the excessive requirement to lock. Furthermore, since there is no feedback mechanism in the duty cycle correction circuit 100, the delay period between output delayed corrected clock signal CLKOUT and the reference clock signal CLKIN is not traceable, causing inconvenience.